Scan chain operation

Scan chain is used to find stuck at faults in the design, it involves 3 stages:

• Shift-In
• Capture
• Shift-Out

In the last post we have discussed about the Scan chain, For better understanding of this post i will recommend you to visit my previous blog on Scan chain.

Lets discuss each stage one by one

Shift-IN
Let us consider the circuit shown in figure 1 to demonstrate how the scan chain functions,having 7 primary inputs (including clk & Scan_enable), assuming output of AND gate SA-0

• When SE = 0, it will act in normal mode & Scan flops will  get the input from the D pin of mux which has connected to the logic cone.
• When SE = 1, flops will get input from T1 pin of mux, the output of one flop is connected to next input of flop acting as a shift register.

As we can see that we don’t have direct controlability on the input pins of faulty gate, we have to use scan chain to pass the test vectors to it.
                                   Inputs of faulty AND gate =  Q_FF1 + Q_FF3

Figure 1

By enabling Scan enable (SE =1) if we pass “101” (test vectors) through Scan_in  & shift a pattern using clk , then at the 3^rd clock pulse we will get “11” inputs of faulty gate.See below table

CLk	FF1	FF2	FF3
0	X	X	x
1	1	X	X
2	0	1	X
3	1	0	1

This whole Scan_in cycle phase is known as Shift in.

Capture

This is the second phase in the scan mode operation known as Capture. After the successfully shifting of test vectors in the design we have to capture the output of faulty AND gate.

For this we have to do:
·    Disable the Scan_enable( SE =0)

When SE = 0, flops will act in normal mode ,so during this period the “d” input of the flop gets its input from the output of  combinational logic,i.e FF2  input gets from the output of faulty gate.

·    Apply one clock pulse to latch data Q_FF2

Applied one clock pulse which will latch the FF2 flop data, which we are trying to observe.

Shift-Out

This is the 3^rd phase of scan mode operation in which we will observe the output of FF2. As Q_FF2  is internal to design, we have to enable Scan mode again (SE = 0) which helps in shifting data bit by bit with clk  until it pops out from scan_out.
The number of clock pulses that are to be applied for shifting the value depends on how deep the capturing flop lies in the circuit. Output from scan_out is compared with the expected value , if its not match we can conclude that there is some problem with the element that drives it, i.e if  logic 0 pops out from scan_out we can conclude that Gate is SA-0. Figure 2 shows the sequence of events that take place during scan-shifting & scan-capture.

 Figure 2: Waveform

The same cycle repeat for each and every node where fault can occur.As testing contribute more than 50% cost of chip in which testing time plays a crucial role, so to reduce test time we have to increase the shift frequency but there is a trade off with power dissipation.
During scan mode toggling of flops & combinational logic block will be there which are a part of large scan chain leads to dynamic power dissipation & temperature hotspots around that region which can create some new violating paths.
So testing is done only in low frequency mode by taking care of test time & power dissipation in mind.

Please let me know if you any doubts in this specific post. In the next post we will discuss about the Scan chain length & reordering concept. Stay Blessed :)

What is Scan Chain

Scan chain is a testing  method to detect various manufacturing faults in the silicon. Although many types of manufacturing faults may exist in the silicon,these could be the result of poor processing (process variation) which leads to shorts and opens.These shorts and opens in the transistors known as stuck-at-one (ST-1) or stuck-at-zero (ST-0) faults.
For e.g : Let's consider the 2-input NOR gate, showing below both logical & physical equivalence.
If  output pin of NOR gate (z) is Stuck at 0, how its physical defect look like

Figure 1: Stuck at 0 fault

From Figure 1 we can see that a short circuit path (low resistance path) has been created between the VCC & GND, which makes the output always 0 whatever be the inputs at gate terminal.

How to detect Stuck at fault
Now, how we will identify faults,Taking the above example of  2 input NOR gate, whose output pin (z) is ST-0,all we need to apply a set of input signals which makes the output of NOR gate high, if there is no fault then the output will be high for set of inputs "00" otherwise we can conclude that the gate is faulty!

Figure 2: NOR gate

we don't have to check every input or output for faults, this we can reduce to a lot with fault equivalence & dominance technique that we will discuss later.
So, using Scan we can control the inputs of gates which are inside the chip & observe the output & we determine whether the gate is faulty or not.

Scan Flip Flop
Scan Flip flop is like normal flop but having a difference of  by the fact that multiplexer has been added at the D pin of flip flop,

Figure 3: Scan flip flop

Multiplexer has 2 inputs & 1 Select line, For normal mode TE(Test Enable) of Scan flop will be 0
& it will work as normal flop, for Test mode mode TE = 1 , test vectors will be applied through TI (Test Input ) pin in the design with the help of Automatic test pattern generator.
In Scan mode (test mode) all the flops have been hooked up to form giant shift register , in which output of one flop Q has been connected to the input D pin of next flop,forming a chain of scan registers (Scan chain) which makes easy to check any stuck at fault in the design, but have to take care of chain length & frequency that we will discussed in next post.

• Scan_in: Scan_in is the pin name which is connected to the input of the first scan flop in the scan chain to pass the test vectors (series of 1's or 0's)
• Scan_out : The output pin through which shifted pattern comes out.
• Scan_enable : Through which we can enable or disable the Scan mode.

In the next post we will discuss about how Scan chain functions. Please let me know if you have any queries in this post.Stay Blessed :)