Parameters required for Good CTS

CTS is one of the most important stages in PnR, CTS QOR decides the timing convergence & Power. In most of the IC design, Clock tree is going to contribute 30-40% of power dissipation. With the Technology advancement Clock tree robustness has become even more critical affecting the overall SOC performance. Before going deep dive into CTS, we will first understand the quality parameters required for good CTS.

• Minimum Latency : Latency is defined as the total time taken by the clock to propagate from the Clock source to the sink pins of flop/sequential device(clk pin of D F/F). We are targeting minimum latency because of less no. of clock cells required in clock path, less power dissipation, less area consumed, more routing resources were available.

• Minimum Skew: Skew is defined as the latency difference b/w two flops. Minimum Skew is helping in timing closure especially Hold timing, but targeting too aggressive minimum skew can be counterproductive because it can create other problems such as overall latency of a design is going to increase, no. of clock cells also going to increase, more uncommon clock path, more power dissipation 

• Minimum Uncommon Clock Path: Registers must have minimum uncommon clock path, as timing derates ( OCV variation) are applied only on uncommon path, if having more uncommon clock path, its become difficult to close design across scenarios (timing). 

• Duty Cycle: Duty cycle is defined as fraction of one period in which a signal is in active state. Maintaining a good duty cycle is also one of the important requirements in CTS because if our duty cycle is going to distort (DCD) it can be a case after some logic we will fail the Min pulse width requirement & face the MPW violation.

• Minimum Power dissipation: To reduce the power dissipation, we will do certain things like clock gating at architectural level & more tighter constraints related DRV’s.

• Signal Integrity: As clock net having very high switching activity, having more prone to noise & Em violation, we will construct the clock tree with NDR rules (double width-double spacing) or whatever the routing rules defined for clock net. Increasing space helps in reducing parasitic cap & increasing width helps in addressing EM.