ICG Optimization

In the previous post we have read about ICG Enable timing problem, to overcome the problem we use ICG optimization technique in pre-cts stage.
ICG optimization is executed during place stage & performs

• Dummy -CTS
• ICG Splitting
• Clock aware placement

Dummy CTS

In Dummy CTS ,it will build a Dummy clock tree to identify the critical ICG, calling it as dummy clock because in cts stage tool will build the actual clock tree by discarding the dummy one 

Benefits of dummy cts are:

• Accurately determine the ICG enable critical timing paths with the help of Dummy cts
• Accurate data path optimization of timing critical ICG enable paths in place stage.
• Effective ICG splitting & clock aware placement (discuss below).

One thing should be taken care of that we have to apply all cts related settings like clock tree exceptions, NDR rules, layers, etc before running place stage in order to correlate Dummy cts & actual cts  clock tree as much as possible for optimum ICG optimziation .

ICG Splitting

After Dummy CTS, ICG optimization perform ICG splitting, we know that if ICG cell is driving multiple reg , it will increase the ICG downstream latency lead to more enable timing critical paths.

Tool identify the Critical ICG's in Dummy cts & do ICG splitting i.e instantiate one ICG into many ICG's & place them near to the reg they drive to reduce ICG downstream latency for better ICG enable timing.

ICG splitting is timing driven means only ICG's with enable timing violations will split.

Figure 1: ICG Splitting

Clock aware Placement

In last stage of ICG optimization tool will do clock aware placement i.e after timing driven splitting of ICG, tool will place the ICG's with critical enable timing  near to register clusters(as shown in figure1).

One thing to note that ICG optimization may increase dynamic power dissipation in our design.
Let me know if you have any doubts .Stay Blessed!!