Different Types of Clock Tree Structure

In the Last post , we had discuss about the Parameters required for good CTS . In this post we will discuss about the Various Clock tree structures widely used in the industry, which having its own merit & demerit.
Lets discuss different Clock Tree Structure one by one

Conventional CTS/Single point CTS: 
Single point CTS is the default choice for most of the designers having lower frequency & lesser no of sinks. As name suggested having single clock source which distribute clock to every corner of design.

Figure 1 : Single Point CTS

                                       
In Single point CTS the point of divergence lie at the clock source, so it shared very large uncommon clock path, more susceptible to OCV variation. In this clock gates are stratergically placed near the source, saving large amount of dynamic power

Advantages:
• Simplicity of Implementation
• Better clock gating, reducing Power dissipation

Disadvantages:
• Higher Insertion delay
• More uncommon clock path, more prone to OCV variation
• Difficult to achieve lower skew, due to asymmetric distribution of sinks.
                                                                   So, conventional CTS is not a good choice for high frequency signals, having high no of sinks (all over core region)

Clock Mesh Structure
As the name suggests it create a dense mesh of  shorted wires which is being driven by mesh drivers to distribute clock in every corner of the design.
In the mesh structure, there will be a network of pre-mesh drivers to drive the clock signal from clock port to input of mesh drivers. The output of all the mesh drivers will be shorted using a metal mesh, which will carry the clock signal across the block using horizontal and vertical metal stripes.

Figure 2: Clock Mesh

                                 
As we can see from Figure 2, mesh drivers are connected to mesh net as multi-driven net. The benefit of the mesh net is that it smoothes out the arrival time differences from the multiple mesh drivers that drive it. If the mesh net is dense enough it require only few stages of clock network (2-3 stages) to route all the sequential element with the clock, which makes the uncommon clock path is very less (path of divergence less), so more prone to OCV variation. In clock Mesh structure power dissipation is going to be high as clock gates cells are inserted after the mesh net, thereby implying clock mesh is always on & switching continuously (as clock gating done at local level only).

Advantages:
• Lower Skew
• Highly tolerant to On-Chip Variation
• Possible to achieve lower insertion delay

Disadvantage:
• More power dissipation (Dynamic)
• More routing resources required for creating mesh
• Difficult to implement

Multi-Source CTS:
Multi-Source CTS is a hybrid approach, between Conventional CTS & Clock Tree Mesh. It involves a global distribution network in form of a sparse mesh or an H-tree with tap points strategically inserted at different locations. These tap points are followed by a local clock tree distribution to route clock from these tap points to the Sequential cell clock end-pins

Advantages:
• More common clock path then Single point CTS , so more prone to OCV variation then Single            Point CTS
• Less routing resources required then Mesh based clock Tree
• Less power Dissipation then Mesh based Clock Tree
• Less insertion delay as compared to Conventional Clock Tree
• Lesser Skew

In last , have tried to conclude all the design metric with different variants of Clock Tree

Design Metric	Single Point CTS	Mesh based CTS	Multi-Source CTS
Power	Low	High	Moderate
Performance	Low	High	Moderate
Area/Routing Resource	Low	High	Moderate
Impact of OCV	High	Low	Moderate

Let me know , in case you have any queries.Stay Blessed !!

Parameters required for Good CTS

CTS is one of the most important stages in PnR, CTS QOR decides the timing convergence & Power. In most of the IC design, Clock tree is going to contribute 30-40% of power dissipation. With the Technology advancement Clock tree robustness has become even more critical affecting the overall SOC performance. Before going deep dive into CTS, we will first understand the quality parameters required for good CTS.

• Minimum Latency : Latency is defined as the total time taken by the clock to propagate from the Clock source to the sink pins of flop/sequential device(clk pin of D F/F). We are targeting minimum latency because of less no. of clock cells required in clock path, less power dissipation, less area consumed, more routing resources were available.

• Minimum Skew: Skew is defined as the latency difference b/w two flops. Minimum Skew is helping in timing closure especially Hold timing, but targeting too aggressive minimum skew can be counterproductive because it can create other problems such as overall latency of a design is going to increase, no. of clock cells also going to increase, more uncommon clock path, more power dissipation 

• Minimum Uncommon Clock Path: Registers must have minimum uncommon clock path, as timing derates ( OCV variation) are applied only on uncommon path, if having more uncommon clock path, its become difficult to close design across scenarios (timing). 

• Duty Cycle: Duty cycle is defined as fraction of one period in which a signal is in active state. Maintaining a good duty cycle is also one of the important requirements in CTS because if our duty cycle is going to distort (DCD) it can be a case after some logic we will fail the Min pulse width requirement & face the MPW violation.

• Minimum Power dissipation: To reduce the power dissipation, we will do certain things like clock gating at architectural level & more tighter constraints related DRV’s.

• Signal Integrity: As clock net having very high switching activity, having more prone to noise & Em violation, we will construct the clock tree with NDR rules (double width-double spacing) or whatever the routing rules defined for clock net. Increasing space helps in reducing parasitic cap & increasing width helps in addressing EM.