What is Power Gating Technique

Power gating is a technique to reduce Leakage power dissipation by switching off the power of blocks that are in standby mode and switching the power back on when their functionality is required.

In order to switch power off, high Vt transistors are used as switches and placed between the block PG (power and ground) pins and the PG rails.

There are 2 types of power switch

Header switch: Pmos transistor placed between VDD  & power rails.

Footer switch: Nmos transistor is placed between GND & power rails.

Figure 1: Header & Footer Switch

This way the controlled block, is no longer powered by the main power rails (always-on rails), but powered by a switched power rail (collapsible power).

There are multiple aspects designers need to take care of including IR drop, ramp up time, rush current, and the number of power switches added in the design. Lets discuss one by one what it is & what are there significance.

Rush Current: Current drawn by the circuit during power up known as Rush current. As when the circuit powered up all the capacitors is going to charge simultaneously at once, which fetch high amount of current from grid, cause a sudden rush of current which can damage the power switch network.

Usually we use multiple power switch in parallel to divide the power domain supply into small blocks, so by doing this the load on power switch going to reduced which helps in managing rush current

Ramp up Time: The time required for powering up a shutdown domain known as Ramp up time. It should be as less as possible.

IR Drop: To handle rush current power switches are designed to have high channel resistance which leads to high IR drop across the power switch which may cause the degrading of power in the design leads to functionality failure (as minimal supply is going to logic cells).
So, we have to design power switch which should have less IR drop by keeping in mind of Rush current which will be achieved by using two types of power switch one which is used during power up to handle rush current & the second one during normal operation

Leakage Current: As switch cell we used is of high V_T  which also going to contribute in the leakage current, so we have to take care of number of power switches we used in a design.

Requirement is to minimise the ramp up time as much as possible keeping in mind of rush current.

To meet this we have different variety of power switches.Some Power switch cells have one enable control (for gating power) and some have two enable controls. The ones with two enables provide a way to control the ramp up time (power switch network) and rush current at power up. 

This is achieved by carefully designing the cell so that internally, one enable pin is connected to a smaller switch, and the other enable pin is connected to a bigger switch.(2 switches in one power switch)

To power up the switch network the smaller switch is going to turn on first to slowly bring the power supply to expected voltage level keeping rush current under control. Once the circuit gets to certain voltage levels larger switch is turned ON for normal operations of power domain logic cells while manage IR drop.

In the next post we will discuss about some power switch chain style to reduce Power Switch Rush Current. Stay Blessed :)